High speed raster image processors (RIP's) capable of driving all points addressable printers at rates of 60 pages per minute and more are needed for driving todays high volume laser printers. An example of a RIP architecture useful for driving a high speed printer is shown in U.S. Pat. No. 4,722,064 issued Jan. 26, 1988 to Suzuki. FIG. 2 is a block diagram illustrating this prior art RIP architecture. The raster image processor generally designated 10 includes an interface 12, a control processing unit 14, a print controller 16, an element memory 18, and an image processor 20, all connected via a general purpose bus 22. The interface 12 receives print instructions from a host computer (not shown) according to a standard protocol. The central processing unit 14 is a programmed microprocessor that controls the overall operation of the RIP such as fetching print instructions from the host computer through interface 12 and storing them in element memory 18, controlling the processing of print instructions into raster information by image processor 20, and controlling the operation of a printer 24 via printer controller 16. The printer 24 for example can be an electrophotographic laser printer.
The printer controller 16 is a sequencer that controls the printer 24 by providing signals such as paper feed, advancing the photo receptor etc. The image processor 20 is a micro program element processor for converting print instructions read from the print element memory 18 into raster bitmap data, and storing the bitmap data in a raster memory 24a or 24b. The image processor 20 is connected to the raster memory 24a and 24b by a high speed bus 26. The raster bitmap data is supplied to the printer 24 by a video interface 28. The video interface is connected to the raster memories 24a and 24b by a second high speed bus 30. Although the prior art RIP architecture shown in FIG. 2 performs well up to a certain speed, there is a bottle neck that constrains further increases in speed as faster marking engines have been developed, and need to be driven at their maximum capable rate. This bottle neck is due to the fact that the general purpose bus 22 carries both overhead commands for controlling the operation of the RIP, and data transfer between the element memory 18 and image processor 20. Thus, control commands from the CPU 14 to the printer controller 16, image processor 20 and element memory 18 must time share the bus 22 with data transferred from the element memory 18 to the image processor 20, thereby limiting the maximum effective speed of operation of the RIP.